tag:blogger.com,1999:blog-5246987755651065286.post7979980319395925147..comments2024-02-22T16:15:42.388-08:00Comments on cbloom rants: 01-25-09 - Low Level Threading Junk Part 2.02cbloomhttp://www.blogger.com/profile/10714564834899413045noreply@blogger.comBlogger3125tag:blogger.com,1999:blog-5246987755651065286.post-26237088883999160212009-01-30T00:53:00.000-08:002009-01-30T00:53:00.000-08:00BTW...As far as future processors with very large ...BTW...As far as future processors with very large numbers of cores, people are talking relaxing cache coherency guarantees. Maybe only some cores will be coherent with respect to others...<BR/><BR/>It may okay though... There are some processors with large numbers of cores today that use directory based cache coherency systems...Brianhttps://www.blogger.com/profile/18061165495812067689noreply@blogger.comtag:blogger.com,1999:blog-5246987755651065286.post-57743626144117130352009-01-30T00:46:00.000-08:002009-01-30T00:46:00.000-08:00Having atomic data types does make some sense. It...Having atomic data types does make some sense. It could provide some static checking that someone doesn't perform non-atomic operations in an unsafe way on the data.<BR/><BR/>A lot of researchers are looking at implementation transactional memory models to replace locking. The devil is of course getting the overhead low enough to work.Brianhttps://www.blogger.com/profile/18061165495812067689noreply@blogger.comtag:blogger.com,1999:blog-5246987755651065286.post-91995117041639646522009-01-28T10:45:00.000-08:002009-01-28T10:45:00.000-08:00I think it must be that the caches talk to each ot...<I>I think it must be that the caches talk to each other and they must invalidate pages in temporal order or something.</I><BR/><BR/>Old school, there's a shared bus, and they implement <A HREF="http://en.wikipedia.org/wiki/Bus_sniffing" REL="nofollow">bus snooping</A>. However, once you start having, say, huge quanties of cores without a single temporally-coherent bus, I have no clue how the magic happens.<BR/><BR/>I wonder if future processors will be more Alpha-like, or if everyone will agree that that's just too nuts.<BR/><BR/>(The thing about an implementation that's Alpha-like isn't just the suckiness if you don't fence; if the thing is being that crazily out-of-order in its cache handling, it seems like the fences are going to be really expensive since it's going to have to force the cache to come to a consistent state--even while other stuff is happening in adjacent cores.)Anonymousnoreply@blogger.com